rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1959 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 pll/multibit - dac functional block diagram osc pll circuit serial control interface vo ltag e reference mclk ad1959 xin loop filters clock outputs control data input multibit sigma-delta modulator interpolator 8 f s atten/mute dac output buffer serial data interface multibit sigma-delta modulator atten/mute dac output buffer 16-/20-/24- bit digital data input 3 l r analog outputs reset mute zero flag pll supply digital supply analog supply 3 2 2 3 23 interpolator 8 f s xout features 5 v stereo audio dac system accepts 16-bit/20-bit/24-bit data supports 24 bits, 192 khz sample rate accepts a wide range of sample rates including: 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, and 192 khz multibit sigma-delta modulator with data directed scrambling single-ended output for easy application C94 db thd + n 108 db snr and dynamic range 75 db stopband attenuation clickless volume control hardware and software controllable clickless mute serial (spi) control for: serial mode, number of bits, sample rate, volume, mute, de-emphasis and output phase digital de-emphasis processing for 32 khz, 44.1 khz, and 48 khz sample rates programmable dual fractional-n pll clock generator 27 mhz master clock input/oscillator generated system clocks sclk0: 33.8688 mhz sclk1: 384/256 f s (32 khz/44.1 khz/48 khz/88.2 khz/ 96 khz) sclk2: 512 f s (32 khz/44.1 khz/48 khz/88.2 khz/ 96 khz)/22.5792 mhz better than 100 ps rms clock jitter flexible serial data port with right-justified, left- justified, i 2 s-compatible, and dsp serial port modes 28-lead ssop plastic package applications dvd, cd, home theater systems, automotive audio systems, sampling musical keyboards, digital mixing consoles, digital audio effects processors product overview the ad1959 is a complete high-performance single-chip stereo digital audio playback system. it is comprised of a multibit sigma- delta modulator, digital interpolation filters, and analog output drive circuitry with an on-board dual pll clock generator. other features include an on-chip stereo attenuator and mute, programmed through an spi-compatible serial control port. the ad1959 is fully compatible with all known dvd formats including 96 khz and 192 khz sample frequencies and 24 bits. it also is backwards-compatible by supporting 50 s/15 s digital de-emphasis for ?edbook?compact discs, as well as de-em phasis at 32 khz and 48 khz sample rates. the ad1959 has a simple but flexible serial data input port that allows for glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers, and sample rate converters. the ad1959 can be configured in left-justified, i 2 s, right-justified, or dsp serial-port-c ompatible modes. it can support 16, 20, and 24 bits in all modes. the ad1959 accepts serial audio data in msb first, tw o?-complement format, and o perates from a single 5 v power supply. it is fabr icated on a single monolithic inte grated circuit and housed in a 28-lead ssop package for operation over the temperature range ?0 c to +105 c.
rev. 0 C2C ad1959?pecifications test conditions unless otherwise noted supply voltages (avdd, dvdd) 5.0 v ambient temperature 25 c input clock 12.288 mhz input signal 996.11 hz ?.5 db full scale input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 20 bits load capacitance 100 pf load impedance 47 k ? input voltage hi 3.5 v input voltage lo 0.8 v analog performance min typ max unit resolution 24 bits signal-to-noise ratio (20 hz to 20 khz) no filter (stereo) 105 db with a-weighted filter (stereo) 108 db dynamic range (20 hz to 20 khz, ?0 db input) no filter (stereo) 105 db with a-weighted filter (stereo) 101 108 db total harmonic distortion + noise (stereo) ?4 ?1 db pll performance master clock input frequency 27 mhz generated system clocks sclk0 33.8688 mhz sclk1 12.288 mhz sclk2 22.5792 mhz jitter (sclk0 and sclk1) 85 125 ps rms analog outputs single-ended output range ( full scale) 3.17 v p-p output capacitance at each output pin 2 pf v ref (filtr) 2.34 2.39 2.44 v gain error ? 2.0 +5 % interchannel gain mismatch ?.15 0.015 +0.15 db gain drift 150 250 ppm/ c dc offset ?5 ? +15 mv out-of-band energy (0.5 f s to 100 khz) ?0 db interchannel crosstalk (eiaj method) ?20 db interchannel phase deviation 0.1 degrees de-emphasis gain error 0.1 db notes performance of right and left channels is identical (exclusive of the interchannel gain mismatch and interchannel phase deviati on specifications). specifications subject to change without notice. digital i/o (?0 c to +105 c ) min typ max unit input voltage hi (v ih ) except xin 2.2 v input voltage hi (v ih ) xin 2.7 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 2.4 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a high level output voltage (v oh ) i oh = 1 ma 2.0 v low level output voltage (v ol ) i ol = 1 ma except xout 0.4 v low level output voltage (v ol ) i ol = 1 ma xout 1.2 v input capacitance 20 pf specifications subject to change without notice.
rev. 0 C3C ad1959 temperature range min typ max unit specifications guaranteed 25 c functionality guaranteed ?0 +105 * c storage ?5 +150 c notes * 105 c ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. derate to 85 c for 2-layer board, 2 oz. layers. specifications subject to change without notice. power min typ max unit supplies voltage, analog digital pll 4.50 5 5.50 v analog current 36 42 ma digital current 28 34 ma pll current 27 32 ma dissipation operation ?all supplies 455 540 mw operation ?analog supply 180 mw operation ?digital supply 140 mw operation ?pll supply 135 mw specifications subject to change without notice. digital filter characteristics sample rate (khz) pass band (khz) stop band (khz) stopband attenuation (db) pass-band ripple (db) 44.1 dc?0 24.1?28.7 75 0.0002 48 dc?1.8 26.23?58.28 75 0.0002 96 dc?9.95 56.9?27.65 75 0.0005 192 dc?7.2 117?27.65 60 0/?.04 (dc?1.8 khz) 0/?.5 (dc?5.4 khz) 0/?.5 (dc?7.2 khz) specifications subject to change without notice. group delay chip mode group delay calculation f s group delay unit int8 mode 24.625/f s 48 khz 513 s int4 mode 15.75/f s 96 khz 164 s int2 mode 14/f s 192 khz 72.91 s specifications subject to change without notice. digital timing (guaranteed over ?0 c to +105 c, avdd = dvdd = 5.0 v 10%) min unit t dmp mclk period (fmclk = 256 flrclk) 54 ns t dml mclk lo pulsewidth (all modes) 15 ns t dmh mclk hi pulsewidth (all modes) 10 ns t dbh bclk hi pulsewidth 7 ns t dbl bclk lo pulsewidth 12 ns t dbp bclk period 60 ns t dls lrclk setup 20 ns t dlh lrclk hold (dsp serial port mode only) 20 ns t dds sdata setup 15 ns t ddh sdata hold 10 ns t rstl rst lo pulsewidth 15 ns specifications subject to change without notice.
rev. 0 ad1959 C4C absolute maximum ratings * dvdd to dgnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v avdd to dgnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v digital inputs . . . . . . . . . . dgnd ?0.3 v to dvdd + 0.3 v analog inputs . . . . . . . . . . agnd ?0.3 v to avdd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to + 0.3 v reference voltage . . . . . . . . . . . . . . . . . . . . . (avdd + 0.3)/2 soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. package characteristics ja (thermal resistance) junction-to-ambient 109.0 c/w typ (2-layer board) ja (thermal resistance) junction-to-ambient 78.58 c/w typ (4-layer board? signal, 2 planes) ja (thermal resistance) junction-to-case 39.0 c/w typ ordering guide model temperature package description package option ad1959yrs ?0 c to +105 c 28-lead small outline package rs-28 ad1959yrsrl ?0 c to +105 c 28-lead small outline package rs-28 on 13" reels eval-ad1959eb evaluation board pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad1959 sclk2 sclk1 xin xout mclk sclk0 dgnd cclk clatch reset lrclk dvdd sdata bclk pvdd pgnd lf0 lf1 agnd0 outr fltr cdata mute zero filtb agnd1 outl avdd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1959 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 ad1959 C5C pin function descriptions pin input/output mnemonic description 1 i cclk control clock input for control data. control input data must be valid on the rising edge of cclk. cclk may be continuous or gated. 2i clatch latch input for control data. 3i reset reset. the ad1959 is placed in a reset mode when this pin is held lo. the serial control port registers are reset to their default values. set hi for normal operation. 4 i lrclk left/right clock input for input data. must run continuously. 5 i bclk bit clock input for input data. need not run continuously; may be gated or used in a burst fashion. 6 i sdata serial input, msb first, containing two channels of 16/20/24 bits of two?- complement data per channel. 7 i dvdd digital power supply connect to digital 5 v supply. 8 i dgnd digital ground. 9 o sclk0 33.8688 mhz clock output. 10 i/o mclk 27 mhz master clock output/256 f s dac clock input. 11 o xout 27 mhz crystal oscillator output. 12 i xin 27 mhz crystal oscillator/external clock input. 13 o sclk1 256/384 f s output. 14 o sclk2 512 f s /22.5792 mhz output. 15 pvdd pll power supply. connect to pll 5 v supply. 16 pgnd pll ground. 17 lf0 pll0 loop filter. 18 lf1 pll1 loop filter. 19 agnd0 analog ground. 20 o outr right channel positive line level analog output. 21 o filtr voltage reference filter capacitor connection. bypass and decouple the voltage reference with parallel 10 f and 0.1 f capacitors to agnd. 22 i agnd1 analog ground. 23 o outl left channel line level analog output. 24 avdd analog power supply. connect to analog 5 v supply. 25 filtb filter capacitor connection, connect 10 f capacitor to agnd. 26 o zero zero flag output. this pin goes hi when both channels have zero signal input for more than 1024 l/r clock cycles. 27 i mute mute. assert hi to mute both stereo analog outputs. deassert lo for normal operation. 28 i cdata serial control input, msb first, containing 16 bits of unsigned data per channel.
rev. 0 ad1959 C6C functional description dac the ad1959 has two dac channels arranged as a stereo pair with single-ended analog outputs. each channel has its own independently programmable attenuator, adjustable in 16384 linear steps. digital inputs are supplied through a serial data input pin, sdata, a frame clock, lrclk and a bit clock, blck. each analog output pin sits at a dc level of v ref , and swings 1.585 v for a 0 db digital input signal. a single op amp third- order external low-pass filter is recommended to remove high-frequency noise present on the output pins. the output phase can be changed in an spi control register to accommo- date inverting and noninverting filters. note that the use of op amps with low slew rate or low bandwidth may cause high fre- quency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the filtd and filtr pins should be bypassed by external capacitors to ground. the filtd pin is used to reduce the noise of the internal dac bias circuitry, thereby reducing the dac output noise. the voltage at the v ref pin, filtr (~2.39 v) can be used to bias external op amps used to filter the output signals. the dac master clock frequency is 256 f s for the 32 khz?8 khz range. for the 96 khz range this is 128 f s . it is supplied inter- nally from the pll clock system when mclk mode is set to output in the pll control register. when the mclk mode is changed to input, it must be supplied from an external source connected to mclk. the output from the 27 mhz pll clock is disabled in this case. pll clock system the pll clock system operates from a 27 mhz master clock supplied by the on-board crystal oscillator or an external source connected to xin. with the mclk mode set to output, the 27 mhz clock is buffered out to the mclk pin. when set to input, the mclk is the 256 f s master clock input for the dac. sclk0 produces a 33.8688 mhz output, sclk1 is intended to be used as a master audio clock and will be a multiple of the sample rate set in the pll control register. it can be set to 256 f s or 384 f s using bit 5 and to 512 f s or 768 f s , with bit 4. sclk2 can be set to a constant 22.5792 mhz (512 44.1 khz) or 512 f s by bit 3 of the pll control register. please note that sclk2 is intended to operate a dsp and does not meet the jitter specific ations stated under analog performance. all the generated clocks can be set to 1/2 their nominal rate by setting ref_div2, bit 8 in the pll control register. reset reset will set the control registers to their default settings. the chip should be reset on power-up. after reset is deasserted, the part will come out of reset on the next rising lrclk. serial control port the ad1959 has an spi-compatible control port to permit programming the internal control registers for the pll and dac. the dac output levels may be independently pro grammed by means of an internal digital attenuator adjustable in 16384 linear steps. the spi control port is a 3-wire serial control port. the format is similar to the motorola spi format except the input data word is 16 bits wide. max serial bit clock frequency is 8 mhz and may be completely asynchronous to the pll system or the dac. figure 1 shows the format of the spi signal. note that the cclk can be gated or continuous, clatch should be low during the 16 active clocks. clatch cclk cdata d0 d15 d14 figure 1. format of spi signal
rev. 0 ad1959 C7C power supply and voltage reference the ad1959 is designed for five-volt supplies. separate power supply pins are provided for the analog, digital, and pll sec- tions. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board. for best performance it is recommended that the analog supply be separate from the digital and pll supply. it is recommended that all supplies be isolated by ferrite beads in series with each supply. it is expected that the digital and pll sections will be run from a common supply but isolated from one another. it is important that the analog supply be as clean as possible. the internal voltage reference is brought out on pin 21 (filtr) and should be bypassed as close as possible to the chip with a parallel combination of 10 f and 100 nf the reference voltage may be used to bias external op amps to the common-mode voltage of the analog output signal pins. the current drawn from the v ref pin should be limited to less than 50 a. serial data ports ?data format the dac serial data input mode defaults to i 2 s. by changing bits 4 and 5 in the dac control register, the mode can be changed to rj, dsp, or lj. the word width defaults to 24 bits but can be changed by programming bits 8 and 9 in the dac control register. figure 2 shows the serial mode formats. lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel left channel right channel msb msb msb msb msb msb msb msb lsb lsb lsb lsb lsb lsb lsb lsb left-justified mode ?16 to 24 bits per channel 1 2 s mode ?16 to 24 bits per channel right-justified mode ?select number of bits per channel dsp mode ?16 to 24 bits per channel 1/f s notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. figure 2. stereo serial modes
rev. 0 C8C c00660C2.5C4/01(0) printed in u.s.a. ad1959 outline dimensions dimensions shown in inches and (mm). printed in u.s.a. 28-lead small outline package (ssop) (rs-28) 0.009 (0.229) 0.005 ( 0.127 ) 0.03 (0.762) 0.022 (0.558) 8 0 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) seating plane 0.0256 (0.65) bsc 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 15 14 1 0.407 (10.34) 0.397 (10.08) pin 1 table i. dac control register bit 11:10 bit 9:8 bit 7 bit 6 bit 5:4 bit 3:2 bit 1:0 interpolation serial data serial data de-emphasis spi register factor width output phase soft mute format filter address 00 = 8 * 00 = 24 bits * 0 = noninverted * 0 = no mute * 00 = i 2 s * 00 = none * 01 01 = 4 01 = 20 bits 1 = inverted 1 = muted 00 = right justified 01 = 44.1 khz 10 = 2 10 = 16 bits 10 = dsp 10 =32 khz 11 = not allowed 11 = 16 bits 11 = left justified 11 = 48 kh z * default setting. table ii. dac volume registers b it 15:2 bit 1:0 volume spi register address 14 bits, unsigned 00 = left volume 14 bits, unsigned 10 = right volume default is full volume. table iii. pll control register bit 11 bit 10 bit 9 bit 8 bit 7:6 bit 5 bit 4 bit 3 bit 2 bit 1:0 pll2 pll1 xtal ref_div2 spi power- power- power- power- sclk1 sclk2 mclk register down down down down f s select double select mode address 0 = on * 0 = on * 0 = on * 0 = no div * 00 = 48 khz * 0 =256 * 0 = f s * 0 = 512 4.1 khz * 0 = output * 11 1 = power- 1 = power- 1 = power- 1 = div by 2 01 = not 1 =384 1 = 2 f s 1 = 512 f s 1 = input down down down allowed 10 = 32 khz 11 = 44.1 khz * default setting.
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